As an operating frequency of a semiconductor memory device has been increasing, a timing margin required for synchronizing an internal signal with an external signal and for detecting/sampling/latching the internal signal has been gradually decreased. Although the memory, such as a Dual Data-Rate (DDR) memory, may support high-speed successive operations, the circuit that supplies power may not operate properly at such frequencies. In particular, the power level may have increased noise or the level of the power may be reduced during such operations. The increase of the power noise increases the variation in the delay in generating a signal (i.e., the delay variation width of the signal). Such a problem may become a factor in the operation of the semiconductor memory at a high frequency.
Particularly, in a circuit for controlling Column Address Strobe (CAS) latency time, that is time interval from inputting of a column address to outputting of predetermined data based on the input column address, the increase of the delay variation width of the signal becomes a factor that induces an erroneous operation of data output timing.
FIG. 1 is a schematic block diagram illustrating a conventional latency control circuit. Referring to FIG. 1, the conventional latency control circuit includes a command decoder 100, a latency signal generator 110, a switching unit 120 and an output buffer 130. The command decoder 100 analyzes an internal command CMD to output an internal activation command PACT synchronized with an external clock ECLK, an internal read command PREAD or an internal write command PWRITE. In addition, the latency signal generator 110 receives the command signals PACT, PREAD or PWRITE to output a latency signal delayed by a predetermined period according to latency information set by a Mode Register Set (MRS), etc. In addition, the switching unit 120 outputs a PTRST signal synchronized with an internal clock ICLK1 which is an output of a delay locked loop (DLL). The PTRST signal is used as a signal for activating the output buffer 130. Furthermore, the output buffer 130 is activated by the activating signal PTRST and receives an internal clock ICLK2 and an output DO from an output latch to output an output data DOUT.
FIG. 2 is a timing diagram illustrating operations of the conventional latency control circuit. Referring to FIG. 2, an internal command signal READ1 detected at a rising edge of a clock CLK1 is converted into the command signal PREAD by the command decoder 100. An internal command signal READ2 detected at the rising edge of a clock CLK4 is converted into the command signal PREAD by the command decoder 100. The activated command signal PREAD is delayed by a predetermined clock at the latency signal generator 110, and thereafter is output as the latency signal. In addition, since the first delay operation occurs at the rising interval of the signal PREAD based on the internal command signal READ1, the power noise is relatively insignificant. However, at the rising interval of the signal PREAD based on the internal command signal READ2, the power noise problem occurs so that VDD and VCC lines may not support the rising of the latency signal due to the relatively high frequency of the external clock ECLK.
In other words, the time interval between read operations may be so short that the levels of VDD and VCC may be reduced by the high frequency switching of the circuits that perform the read operations. The transition speed of the latency signal from a non-active state to art active state may be slowed since the operational speed of the circuits of the latency controller 210 is reduced due to the effects on VDD and VCC. Therefore, the latency signal is delayed. The latency signal is more sensitive to the power noise since the latency signal passes through more circuits of the memory device than the internal clock ICLK1. The internal clock ICLK1 signal is less sensitive to the power noise than the latency signal since the internal clock ICLK1 signal passes through less circuits of the memory device than the latency signal. Namely, the effect of the power noise is not large when the first read command READ1 is inputted to the command decoder 100, however, the effect of the power noise is large when the second read command READ2 is inputted to the command decoder 100 because of the increased delay of the latency signal, which may mean the data read from the memory during at least READ2 is unnecessarily delayed or even missed. For example, in a normal operation, the latency signal may be valid after the rising edge of clock CLK8 of the external clock ECLK, however the latency signal may be valid after the P sing edge of clock CLK9 due to the delay caused by the power noise.
The latency signal, delayed by the power noise, is input to the switching unit 120, and the switching unit 120 synchronizes the delayed latency signal with the internal clock ICLK1 to generate the PTRST signal which is an output buffer activating signal. The PTRST signal that is generated based on the first internal command signal READ1 is activated at the rising edge of a clock CLK6. However, the PTRST signal that is generated based on the internal command READ2 is activated at the rising edge of a clock CLK10 owing to the power noise. The output buffer 130 is activated based on the PTRST signal. In a normal case, the output data DOUT related to the internal command READ2 is initiated to be output at the rising edge of the clock CLK9. However, in fact, the output data DOUT is initiated to be output at the rising edge of the clock CLK10.
In FIG. 2, a DDR2 mode operation in which the 4-bit pre-fetch is performed upon input and output of the data is explained as an example. However, the delay problem of the output data due to the power noise may occur in any memory device that operates at high frequency.